Thin Film Transistor Structure

ABSTRACT

A thin film transistor (TFT) structure is provided. The TFT comprises a gate, a first electrode, a second electrode, a dielectric layer, and a channel layer. By overlapping the area between the first electrode and the gate, the TFT structure acquires a parasitic capacitor that is unaffected by manufacture deviations. Therefore, the TFT needs no compensation capacitor, thereby, increasing the aperture ratio of the TFT.

CROSS-REFERENCES TO RELATED APPLICATIONS

This is a divisional application of patent application Ser. No.11/849,593 filed on Sep. 4, 2007, now allowed. The prior applicationSer. No. 11/849,593 claims the benefit of Taiwan Patent Application No.095146465 filed on Dec. 12, 2006, the disclosures of which areincorporated herein by reference in their entirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a TFT structure; specifically, itrelates to a TFT structure for use in a TFT liquid crystal display.

2. Descriptions of the Related Art

In recent years, flat panel displays have gradually replacedconventional cathode ray tube displays. Current flat panel displaysinclude: organic light-emitting diodes displays (OLEDs), plasma displaypanels (PDPs), liquid crystal displays (LCDs), field emission displays(FEDs), etc. An essential component of these flat panel displays is thethin-film transistor (TFT), which controls the on and off state of eachpixel.

Stability is important to maintain during the panel manufacturingprocess to ensure good product quality and enhance manufacturing yieldrates. However, during the manufacturing process, varying circumstantialconditions can cause the manufacturing parameters to deviate, resultingin electrical characteristic deviation in each TFT on the panel. Forexample, a parasitic capacitance of each TFT presents differentdistributions depending on the different areas of the panel. Becauseparasitic capacitances can occur all over the panel, non-uniformdistributions of the parasitic capacitances will cause non-uniformdistributions of the voltage jumps, resulting in the flickering of thescreen.

To generally suppress the screen flickering, a compensating capacitorconnected with the TFT has been designed to neighbor the original TFTfor eliminating the effect of the TFT parasitic capacitance caused bythe manufacturing process deviation. However, adding the compensatingcapacitor on the panel takes up space needed for lighting, and decreasesthe aperture ratio (i.e. the ratio between the pixel lighting area andtotal pixel area) accordingly. Moreover, a large compensating capacitorshould not be used because it may result in an over range of the voltagejump.

In view of the above-mentioned issue, it is essential for the industryto provide a transistor structure for effectively reducing the areaoccupied by the compensating capacitors in circuit layouts.

SUMMARY OF THE INVENTION

One objective of this invention is to provide a TFT structure for use ina LCD. The TFT comprises a gate electrode, a first electrode, a secondelectrode, a dielectric layer and a channel layer. The gate electrodeconnects to the LCD scanning line and overlaps with the working area ofthe TFT structure. The first electrode is disposed on two sides of theworking area. The second electrode is disposed in the center of theworking area. The dielectric layer is disposed between the gateelectrode and the working area. The channel layer is disposed under thefirst and the second electrodes and is electrically connected to thefirst and the second electrodes. The first electrode is parallel to thesecond electrode in the working area, which overlaps with the gateelectrode. One of the first electrodes and second electrodes areconnected to the pixel electrode of the LCD, while the other electrodesare connected to the data line of the LCD.

Another objective of this invention is to provide a TFT structure foruse in a LCD. The TFT comprises a gate electrode, a first electrode, asecond electrode, a dielectric layer and a channel layer. The gateelectrode connects to the LCD scanning line and overlaps with theworking area of the TFT structure. The first electrode includes twobranches disposed on the center area of the working area. The secondelectrode includes three branches respectively disposed in the center,as well as two sides of the working area. The dielectric layer isdisposed between the gate electrode and the working area. The channellayer is disposed under the first and the second electrodes and iselectrically connected to the first and the second electrodes. Thebranches of the second electrode are disposed on two sides of thebranches of the first electrode respectively. The first electrode isparallel to the second electrode in the working area, which overlapswith the gate electrode. One of the first electrode and the secondelectrode is connected to the pixel electrode of the LCD, while theothers thereof are connected to the data line of the LCD.

The invention provides stability to the TFT, thereby preventingdeviation and parasitic capacitance in the manufacturing process.Meanwhile, since no extra compensating capacitor is required, theparasitic capacitance will not increase significantly when the TFTstructure area is increased to obtain a higher conduction current.

The detailed technology and preferred embodiments implemented for thesubject invention are described in the following paragraphs accompanyingthe appended drawings for people skilled in this field to wellappreciate the features of the claimed invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating the top view of a firstembodiment of the invention;

FIG. 2 is a schematic diagram of a partial sectional view of the firstembodiment; and

FIG. 3 is a schematic diagram illustrating the top view of a secondembodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a schematic diagram illustrating the top view of a TFTstructure 1 of a first embodiment of the invention is shown. The TFTstructure 1 comprises a primary TFT 11 and an auxiliary TFT 12. Theprimary TFT 11 and the auxiliary TFT 12 are electrically connected toeach other in parallel and share a gate electrode 115. The primary TFT11 comprises a first electrode 111 and a second electrode 112, and bothelectrodes connect to a drain and the source of the primary TFT 11,respectively, wherein the second electrode 112 comprises a horizontalsize, i.e. a width. The auxiliary TFT 12 comprises a third electrode 113and a fourth electrode 114, both connect to the drain and the source ofthe auxiliary TFT 12 respectively. The second electrode 112 electricallyconnects to the fourth electrode 114, while the first electrode 111 andthe third electrode 113 connect to different pixel electrodes (notshown). Meanwhile, the second electrode 112 connects to a data line (notshown). In this embodiment and the following embodiment, the onlydifference between the source and the drain is their names forrepresenting providing and receiving terminals of holes or electronswithout any substantial manufacturing process difference.

In this embodiment, within the area overlapping the gate electrode 115,a working area is formed between the channel, which is located betweenthe drain and the source, and the gate electrode 115. The firstelectrode 111 is parallel to the second electrode 112 for maintaininguniformity of the TFT channel lengths. The first electrode 111 overlapswith the gate electrode 115 in a direction parallel to the channel andextends outside the working area. That is, the first electrode 111overlaps with the working area and extends outside the working area. Inthis embodiment, the overlapping area of the first electrode 111 and thegate electrode 115 comprises a horizontal size, i.e. a width, of about1˜10 μm, preferably 4˜7 μm. Meanwhile, the second electrode 112 alsocomprises a horizontal size, i.e. a width, of about 1˜10 μm, preferably4˜7 μm. When the manufacturing process parameters deviate, such as thecase resulting from the misalignment of the manufacturing process forthe first electrode 111, the left side portion of the first electrode111 that extends outside the working area may deviate to the right.Meanwhile, the right side of the first electrode 111 that extendsoutside the working area may deviate to the right synchronously.Consequently, the total overlap area of the first electrode 111 remainsthe same. Similarly, the total overlap area of the first electrode 111and the gate electrode 115 remains the same as well. The capacitancevalue of the flat type capacitors is decided by the overlapping areabetween the upper and lower electrode of the capacitor and thedielectric layer therebetween. Thus, the total overlap between the firstelectrode 111 and the gate electrode 115 remains constant, and as aresult, the parasitic capacitance between the gate and the drain of theprimary TFT 11 is stable and not affected from the deviation generatedfrom the manufacturing process.

Moreover, in this embodiment, the auxiliary TFT 12 also relies on thestructure to maintain stable parasitic capacitance when deviation occursduring the manufacturing process. The fourth electrode 114 and thesecond electrode 112 of the auxiliary TFT 12 are connected directly. Inthe horizontal extension direction overlapping the working area and thethird electrode 113 of the auxiliary TFT 12, the gate electrode 115comprises an indented shape so that the center area does not overlapwith the gate electrode 115. Only the two sides of the third electrode113 and the gate electrode 115 form two overlaps when the thirdelectrode 113 extends outside the working area. Herein, whenmanufacturing parameter deviation occurs, such as the deviation whichresults from the manufacturing misalignment of the third electrode 113,the whole third electrode 113 will be synchronously deviated.Consequently, the total overlap area of the first electrode 113 and thegate electrode 115 does not change and the parasitic capacitance betweenthe gate and the drain of the auxiliary TFT 12 stay stable without beingaffected by the deviation generated during the manufacturing process.

In this embodiment, the primary objective of the first electrode 111 andthe third electrode 113 is to maintain that the overlapping areaoverlapped by the electrodes 111, 113 and the gate electrode 115 willnot be affected by the manufacturing process deviation. Consequently,the first electrode 111 and the third electrode 113 have to be designedto partially overlap with the gate electrode 115 and extend outside thegate electrode 115. In this embodiment, the first electrode 111 and thethird electrode 113 extend out in a direction parallel to the channel.For different layouts, the first electrode 111 and the third electrode113 can extend out in the direction normal to the channel as well.

Meanwhile, since no extra compensating capacitor is required, theparasitic capacitance will not increase significantly when the TFTstructure area is enlarged to obtain a higher conduction current.

FIG. 2 is a cross-sectional view of the primary TFT 11 sectioned alongan AA′ line in FIG. 1, wherein a silicon nitride layer 116 is locatedbetween the gate electrode 115 and the working area 118. The siliconnitride layer 116 acts as a dielectric layer, while the channel layer isfound beneath the first electrode 111 and the second electrode 112. Inthis embodiment, the channel layer can be an amorphous silicon layer 117electrically connected to the first electrode 111 and the secondelectrode 112 to provide a channel for carriers flow. The auxiliary TFT12 is similar to the primary TFT 11 in cross-sectional structure.

FIG. 3 is a schematic diagram illustrating the top view of the TFTstructure 3 of the second embodiment of the invention. The TFT structure3 comprises a primary TFT 31 and an auxiliary TFT 32. The primary TFT 31and the auxiliary TFT 32 are also electrically connected to each otherin parallel and share a gate electrode 315, wherein the primary TFT 31comprises a first electrode 311 and a second electrode 312, whichconnect to the drain and source of the primary TFT 31 respectively.Similarly, the auxiliary TFT 32 comprises a third electrode 313 and afourth electrode 314 which connect to the drain and source of theauxiliary TFT 32, respectively. The second electrode 312 electricallyconnects to the fourth electrode 314, while the first electrode 311 andthe third electrode 313 connects to different pixel electrodes (notshown). Meanwhile, the second electrode 312 connects to a data line (notshown).

In this embodiment, within an area overlapping the gate electrode 315, aworking area is formed between the channel, which is located between thedrain and source, and the gate electrode 315. The first electrode 311comprises two branches disposed in the center of the working area, whilethe second electrode 312 comprises three branches which are respectivelydisposed in the center area and two sides of the working area. Thebranches of the first electrode 311 and the second electrode 312 arearranged in an interleave fashion, i.e. branches of the second electrode312 are respectively disposed on two sides of the branches of the firstelectrode 311 and are parallel to each other for maintaining uniform TFTchannel lengths. The first electrode 311 overlaps with the gateelectrode 315 in a direction normal to the channel and extends outsidethe working area. That is, the first electrode 311 overlaps with theworking area and extends outside the working area. In this embodiment,each branch of the first electrode 311 has a horizontal size, i.e. awidth, of about 1˜10 μm, preferably 4˜7 μm. The center branch of thesecond electrode 312 comprises a horizontal size, i.e. a width, of about1˜10 μm, preferably 4˜7 μm. The two overlapping regions of the secondelectrode 312 and the gate electrode 315, i.e. the two overlapping areasbetween the two side branches and the gate electrode 315, respectively,have a horizontal size, i.e. a width, of about 1˜10 μm, preferably 4˜7μm. When manufacturing process parameters deviate, such as the deviationresulting from the misalignment of the first electrode 311 during themanufacturing process, the left side of the first electrode 311 thatextends outside the working area may deviate to the right. Meanwhile,the right side of the first electrode 311 that extends outside theworking area deviates to the right synchronously. Consequently, thetotal overlapping area between the working area and the first electrode311 remains the same. Similarly, the total overlapping area between thefirst electrode 311 and the gate electrode 315 also remain the same.Like the first embodiment, the total overlap area of the first electrode311 and the gate electrode 315 does not change and the parasiticcapacitance between the gate and the drain of the primary TFT 31 remainstable without being affected by the deviation generated during themanufacturing process.

Furthermore, in this embodiment, the auxiliary TFT 32 also relies on thestructure to maintain a stable parasitic capacitance when deviationoccurs during the manufacturing process. The fourth electrode 314 of theauxiliary TFT 32 and the second electrode 312 are directly connected.The gate electrode 315 of the auxiliary TFT 32 comprises an indentedshape so that the center area portion does not overlap with the gateelectrode 315 and only two sides and the gate electrode 315 form twooverlaps when the third electrode 313 extends outside the working area.Herein, when manufacturing parameter deviation occurs, such as thedeviation resulting from the misalignment of the third electrode 313during the manufacturing process, the whole third electrode 313synchronously deviates. Consequently, the total overlap area of thefirst electrode 313 and the gate electrode 315 does not change and theparasitic capacitance between the gate and the drain of the auxiliaryTFT 32 maintain stability without being affected by the deviationgenerated during the manufacturing process. Meanwhile, since no extracompensating capacitor is required, the parasitic capacitance will notincrease significantly when the TFT structure area is enlarged to obtaina higher conduction current.

In this embodiment, the design rules of the first electrode 311 and thethird electrode 313 are the same as those of the first embodiment; thus,the details are omitted here. Alternatively, the first electrode 311 andthe third electrode 313 can also extend out in the direction parallel tothe channel as well.

The above disclosure is related to the detailed technical contents andinventive features thereof. People skilled in this field may proceedwith a variety of modifications and replacements based on thedisclosures and suggestions of the invention as described withoutdeparting from the characteristics thereof. Nevertheless, although suchmodifications and replacements are not fully disclosed in the abovedescriptions, they have substantially been covered in the followingclaims as appended.

1. A thin film transistor (TFT) structure for a liquid crystal display(LCD) having a scan line a data line, a first pixel electrode and asecond pixel electrode, the thin film transistor comprising: a gateelectrode, connecting to the scan line; a dielectric layer, covering thegate electrode; a first patterned channel layer, disposed on thedielectric layer and above the gate electrode; a second patternedchannel layer, disposed on the dielectric layer and above the gateelectrode adjacent to the first patterned channel layer; a firstelectrode, connected to the data line, the first electrode having afirst portion disposed on a portion of the first patterned channel layerand a second portion disposed on a portion of the second patternedlayer; a second electrode, disposed on another portion of the firstpatterned channel layer and electrically connected to the first pixelelectrode, the second electrode including at least two branchessubstantially parallel to the first portion of the first electrode andextending along a first direction, the branches of the second electrodeand the first portion of the first electrode being alternately disposedon the first patterned channel layer with at least two first channelstherebetween; a third electrode, disposed on another portion of thesecond patterned channel layer and electrically connected to the secondpixel electrode, the third electrode being extending along a seconddirection substantially perpendicular to the first direction, the thirdelectrode and the second portion of the first electrode being disposedon the second patterned channel layer with a second channeltherebetween; wherein a channel width-to-length (W-L) ratio of each ofthe first channels is larger than a channel width-to-length (W-L) ratioof the second channel.
 2. The thin film transistor structure of claim 1,wherein the gate electrode, the dielectric layer, the first patternedchannel layer, the first electrode and the second electrode construct aprimary thin film transistor (TFT) structure.
 3. The thin filmtransistor structure of claim 2, wherein one of the first electrode andthe second electrode is a source electrode of the primary thin filmtransistor structure, and the other one of the first electrode and thesecond electrode is a drain electrode of the primary thin filmtransistor structure.
 4. The thin film transistor structure of claim 1,wherein the gate electrode, the dielectric layer, the first patternedchannel layer, the first electrode and the third electrode construct anauxiliary thin film transistor (TFT) structure.
 5. The thin filmtransistor structure of claim 4, wherein one of the first electrode andthe third electrode is a source electrode of the auxiliary thin filmtransistor structure, and the other one of the first electrode and thethird electrode is a drain electrode of the auxiliary thin filmtransistor structure.
 6. The thin film transistor structure of claim 1,wherein the dielectric layer is made of a material comprising siliconnitride.
 7. The thin film transistor structure of claim 1, wherein thefirst patterned channel layer is made of a material comprising amorphoussilicon.
 8. The thin film transistor structure of claim 1, wherein thesecond patterned channel layer is made of a material comprisingamorphous silicon.
 9. The thin film transistor structure of claim 1,wherein each of the first electrode, the second electrode and the thirdelectrode has a width about 1-10 micrometers.
 10. A pixel structure fora liquid crystal display (LCD), comprising: a scan line a data line, afirst pixel electrode and a second pixel electrode; and a thin filmtransistor, comprising: a gate electrode, connecting to the scan line; adielectric layer, covering the gate electrode; a first patterned channellayer, disposed on the dielectric layer and above the gate electrode; asecond patterned channel layer, disposed on the dielectric layer andabove the gate electrode adjacent to the first patterned channel layer;a first electrode, connected to the data line, the first electrodehaving a first portion disposed on a portion of the first patternedchannel layer and a second portion disposed on a portion of the secondpatterned layer; a second electrode, disposed on another portion of thefirst patterned channel layer and electrically connected to the firstpixel electrode, the second electrode including at least two branchessubstantially parallel to the first portion of the first electrode andextending along a first direction, the branches of the second electrodeand the first portion of the first electrode being alternately disposedon the first patterned channel layer with at least two first channelstherebetween; a third electrode, disposed on another portion of thesecond patterned channel layer and electrically connected to the secondpixel electrode, the third electrode being extending along a seconddirection substantially perpendicular to the first direction, the thirdelectrode and the second portion of the first electrode being disposedon the second patterned channel layer with a second channeltherebetween; wherein a channel width-to-length (W-L) ratio of each ofthe first channels is larger than a channel width-to-length (W-L) ratioof the second channel.